After fiddeling around with some single source files I decided to put all the #includes, prototypes and defines into a new header file. Codebench did the obvious and wrote a new Makefile (and a new project file as well). After that I were not able to compile anything. After some investigation I found the following:

My old (working!) Makefile for the single source file looked like this:

$(BIN): $(OBJ)
#	Debug builds require the -g or -gstabs option in CFLAGS
#	You may also need to move the LDFLAGS variable depending on the contents
	$(CC) $(OBJ) $(LIBS) -o $(BIN) $(CFLAGS) $(LDFLAGS)
	strip $(BIN) -o $(BIN)
 
Example.o: Example.c
	$(CC) -c Example.c -o Example.o $(CFLAGS)

The new generated Makefile for one source and one header file looked like this:

$(BIN): $(OBJ)
#	Debug builds require the -g or -gstabs option in CFLAGS
#	You may also need to move the LDFLAGS variable depending on the contents
	$(CC) -o $(BIN).debug $(OBJ) $(LDFLAGS) $(LIBS)
	strip $(BIN).debug -o $(BIN)
 
Example.o: Example.c header.h
	$(CC) -c Example.c -o Example.o $(CFLAGS)

It doesn't compile, because the "$(CFLAGS)" is missing in the "$(BIN):" part of the new makefile. Further I never specified to do a "Example.debug" binary ("$(BIN).debug").

Any idea where this comes from? AFAIK Codebench uses a standard "make -f" call, but I really don't know where this omitting (or including) of $(CFLAGS) and the binary naming with a ".debug" is controlled...